An accurate low-power DAC for SAR ADCs

A highly energy-efficiency switching procedure for the capacitor-splitting digital-to-analog converter (DAC) is presented for successive approximation register (SAR) analogue-to-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (V
ref
), while the common-mode voltage (V
cm
) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of V
cm
except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%.